/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
 * Copyright 2021-2024 NXP
 */

#ifndef __DT_BINDINGS_SCMI_CLOCK_S32R45_H
#define __DT_BINDINGS_SCMI_CLOCK_S32R45_H

#include <dt-bindings/clock/s32cc-scmi-clock.h>

/* LAX 0 */
#define S32R45_SCMI_CLK_LAX_0_MODULE			S32CC_PLAT_SCMI_CLK(0)
/* LAX 1 */
#define S32R45_SCMI_CLK_LAX_1_MODULE			S32CC_PLAT_SCMI_CLK(1)
/* SPT */
#define S32R45_SCMI_CLK_SPT_SPT					S32CC_PLAT_SCMI_CLK(2)
#define S32R45_SCMI_CLK_SPT_AXI					S32CC_PLAT_SCMI_CLK(3)
#define S32R45_SCMI_CLK_SPT_MODULE				S32CC_PLAT_SCMI_CLK(4)
/* GMAC */
#define S32R45_SCMI_CLK_GMAC1_TS				S32CC_PLAT_SCMI_CLK(5)
/* GMAC1 - SGMII */
#define S32R45_SCMI_CLK_GMAC1_RX_SGMII			S32CC_PLAT_SCMI_CLK(6)
#define S32R45_SCMI_CLK_GMAC1_TX_SGMII			S32CC_PLAT_SCMI_CLK(7)
/* GMAC1 - RGMII */
#define S32R45_SCMI_CLK_GMAC1_RX_RGMII			S32CC_PLAT_SCMI_CLK(8)
#define S32R45_SCMI_CLK_GMAC1_TX_RGMII			S32CC_PLAT_SCMI_CLK(9)
/* GMAC1 - RMII */
#define S32R45_SCMI_CLK_GMAC1_RX_RMII			S32CC_PLAT_SCMI_CLK(10)
#define S32R45_SCMI_CLK_GMAC1_TX_RMII			S32CC_PLAT_SCMI_CLK(11)
/* GMAC1 - MII */
#define S32R45_SCMI_CLK_GMAC1_RX_MII			S32CC_PLAT_SCMI_CLK(12)
#define S32R45_SCMI_CLK_GMAC1_TX_MII			S32CC_PLAT_SCMI_CLK(13)
#define S32R45_SCMI_CLK_GMAC1_AXI				S32CC_PLAT_SCMI_CLK(14)
/* MIPICSI2 0 */
#define S32R45_SCMI_CLK_MIPICSI2_0_CFG			S32CC_PLAT_SCMI_CLK(15)
#define S32R45_SCMI_CLK_MIPICSI2_0_DPHY_ESC		S32CC_PLAT_SCMI_CLK(16)
#define S32R45_SCMI_CLK_MIPICSI2_0_PLL_REF		S32CC_PLAT_SCMI_CLK(17)
#define S32R45_SCMI_CLK_MIPICSI2_0_MODULE		S32CC_PLAT_SCMI_CLK(18)
#define S32R45_SCMI_CLK_MIPICSI2_0_EXT			S32CC_PLAT_SCMI_CLK(19)
#define S32R45_SCMI_CLK_MIPICSI2_0_CTRL			S32CC_PLAT_SCMI_CLK(20)
#define S32R45_SCMI_CLK_MIPICSI2_0_AXI			S32CC_PLAT_SCMI_CLK(21)
/* MIPICSI2 1 */
#define S32R45_SCMI_CLK_MIPICSI2_1_CFG			S32CC_PLAT_SCMI_CLK(22)
#define S32R45_SCMI_CLK_MIPICSI2_1_DPHY_ESC		S32CC_PLAT_SCMI_CLK(23)
#define S32R45_SCMI_CLK_MIPICSI2_1_PLL_REF		S32CC_PLAT_SCMI_CLK(24)
#define S32R45_SCMI_CLK_MIPICSI2_1_MODULE		S32CC_PLAT_SCMI_CLK(25)
#define S32R45_SCMI_CLK_MIPICSI2_1_EXT			S32CC_PLAT_SCMI_CLK(26)
#define S32R45_SCMI_CLK_MIPICSI2_1_CTRL			S32CC_PLAT_SCMI_CLK(27)
#define S32R45_SCMI_CLK_MIPICSI2_1_AXI			S32CC_PLAT_SCMI_CLK(28)
/* MIPICSI2 2 */
#define S32R45_SCMI_CLK_MIPICSI2_2_CFG			S32CC_PLAT_SCMI_CLK(29)
#define S32R45_SCMI_CLK_MIPICSI2_2_DPHY_ESC		S32CC_PLAT_SCMI_CLK(30)
#define S32R45_SCMI_CLK_MIPICSI2_2_PLL_REF		S32CC_PLAT_SCMI_CLK(31)
#define S32R45_SCMI_CLK_MIPICSI2_2_MODULE		S32CC_PLAT_SCMI_CLK(32)
#define S32R45_SCMI_CLK_MIPICSI2_2_EXT			S32CC_PLAT_SCMI_CLK(33)
#define S32R45_SCMI_CLK_MIPICSI2_2_CTRL			S32CC_PLAT_SCMI_CLK(34)
#define S32R45_SCMI_CLK_MIPICSI2_2_AXI			S32CC_PLAT_SCMI_CLK(35)
/* MIPICSI2 3 */
#define S32R45_SCMI_CLK_MIPICSI2_3_CFG			S32CC_PLAT_SCMI_CLK(36)
#define S32R45_SCMI_CLK_MIPICSI2_3_DPHY_ESC		S32CC_PLAT_SCMI_CLK(37)
#define S32R45_SCMI_CLK_MIPICSI2_3_PLL_REF		S32CC_PLAT_SCMI_CLK(38)
#define S32R45_SCMI_CLK_MIPICSI2_3_MODULE		S32CC_PLAT_SCMI_CLK(39)
#define S32R45_SCMI_CLK_MIPICSI2_3_EXT			S32CC_PLAT_SCMI_CLK(40)
#define S32R45_SCMI_CLK_MIPICSI2_3_CTRL			S32CC_PLAT_SCMI_CLK(41)
#define S32R45_SCMI_CLK_MIPICSI2_3_AXI			S32CC_PLAT_SCMI_CLK(42)
/* CTE */
#define S32R45_SCMI_CLK_CTE_REG_INTF			S32CC_PLAT_SCMI_CLK(43)
#define S32R45_SCMI_CLK_CTE						S32CC_PLAT_SCMI_CLK(44)
/* BBE32EP DSP */
#define S32R45_SCMI_CLK_EIM_DSP					S32CC_PLAT_SCMI_CLK(45)
#define S32R45_SCMI_CLK_BBE32EP_DSP				S32CC_PLAT_SCMI_CLK(46)

#endif /* __DT_BINDINGS_SCMI_CLOCK_S32R45_H */
